In recent years, the cache memory has been widely used in order to reduce access time to the main memory and improve the processing performance of the processor.
When data is written into the cache memory from the processor, there is a need to write back from the cache memory to the main memory in order to maintain the consistency of data between the main memory and the cache memory. As a control method for such write back, there exists the write-through method and the write-back method.
In the write-through method, the write operation is performed on both the cache memory and the main memory during the execution of a write instruction from the processor to the cache memory. Since, with the write-through method, a write back penalty occurs every time data is written into the cache memory, the effect on the reduction of memory access time, with respect to the memory write operation, is insignificant.
On the other hand, in the write-back method, the write operation is performed only on the cache memory during the execution of a write instruction, and a write back is performed, from the cache memory to the main memory, just before a dirty line resulting from a cache miss is replaced with new different data. Although, in such write-back method, a write penalty does not occur with every memory write operation, penalties during a cache miss increase as a write back penalty occurs in addition to the load penalty during a cache miss in memory write and memory read operations. Here, load penalty refers to the penalty brought about by the loading of new data from the main memory to the cache memory. Write-back penalty refers to the penalty brought about by writing back data from the cache memory to the main memory.
Conventional technology for reducing such cache miss penalties are disclosed, for example, in patent reference 1 and the like.
According to such conventional technology, in the cache memory in the write-back method, aside from the normal write back operation to the main memory for evicting data from the cache memory, a write back operation which is only for writing back data from the cache memory to the main memory is performed. In the latter operation, first, it is judged whether or not the data of one entry of the cache memory is dirty, and when it is dirty, the data is written back to the main memory. Subsequently, it is verified that the write back concludes normally, and that the data in the cache memory is not changed, and the cache status is assumed to be clean.
In this manner, the cache memory in the conventional technology reduces traffic from the cache memory to the main memory, and improves the performance of the whole system.
Patent Reference 1: Japanese Laid-Open Patent Application No. 6-309231 Publication